FIG. 3 shows a recess structure and a T-shaped gate electrode structure of a prior art field effect transistor. In FIG. 3, reference numeral 1 designates a GaAs substrate. An active layer 2 is disposed on the GaAs substrate 1. A recess 22 is disposed in the active layer 2, and a T-shaped gate electrode 23' is disposed on the recess 22. Reference character w represents the width of the recess, t represents the depth of the recess, a represents the thickness of the active layer 2 below the gate electrode 23', and lg represents the length of the gate electrode 23'.
A production method of the prior art field effect transistor will be described with reference to FIGS. 4(a) to 4(j).
As shown in FIG. 4(a), a nitride film 3 is deposited on the active layer 2 on the substrate 1 by plasma chemical vapor deposition (CVD) and an electron beam resist such as polymethylmethacrylate (PMMA) resist 20 is deposited thereon by spin coating.
Next, as shown in FIG. 4(b), an electron beam 21 irradiates the PMMA resist 20 which is developed to produce an aperture 20a, as shown in FIG. 4(c).
Next, as shown in FIG. 4(d), the nitride film 3 is etched by reactive ion etching (RIE) using the resist 20 as a mask. Thereafter, as shown in FIG. 4(e), the active layer 2 is chemically etched to produce a recess 22.
Thereafter, as shown in FIG. 4(f), the PMMA resist 20 is removed and, as shown in FIG. 4(g), a gate metal 23 is deposited on the entire surface by vapor deposition.
Next, as shown in FIG. 4(h), the pattern of the head of a T-shaped gate is produced utilizing a negative resist 24. As shown in FIG. 4(i), the gate metal 23 is etched by ion milling, thereby producing a gate electrode 23'.
Finally, as shown in FIG. 4(j), the negative resist 24 and the nitride film 3 are removed, thereby producing a recessed T-shaped gate field effect transistor having a T-shaped gate electrode 23' in the recess 22.
The FET is produced with a recessed structure. A portion of the active layer 2 where the gate electrode is to be produced is etched to an active layer thickness a for a corresponding carrier concentration N to obtain a predetermined current value. The recess width w and the recess depth t greatly affect RF performance and the reverse gate breakdown voltage. Further, there is a tendency that as the reverse gate voltage is increased, the RF performance deteriorates. These effects are thought to be caused by broadening of the depletion layer which determines the reverse gate breakdown voltage and the parasitic resistance and parasitic capacitance which have a large influence on RF performance. The parasitic element values vary significantly depending on the recess structure, so that optimization of the recess width w and recess depth t are attempted. However, control of the recess width w and recess depth t is restricted by desired enhancement of breakdown voltage and performance. In the prior art single stage recess structure, concentration of electric fields at the recess edges may arise, thereby failing to reduce the electric field between the gate and drain. On the other hand, to improve the parasitic resistances and capacitances, a T-shaped gate structure is adopted. However, even the adoption of such T-shaped gate structure cannot sufficiently reduce parasitic resistances and capacitances in a single stage recess structure.
As discussed above, in the prior art FET, there are many restrictions on the enhancement of breakdown voltage and that of performance, and it was difficult to reduce the parasitic resistances between the gate and source only by the optimization of the recess width w and the recess depth t of a single stage recess with a T-shaped gate. Further, in such a recessed structure, the electric fields between the gate and drain are unfavorably concentrated at a recess edge.
FIGS. 5(a) to 5(g) show major production steps of a semiconductor device having a two stage recess structure, as disclosed in Japanese Published Patent Application 61-89681. In the figures, reference numeral 31 designates a semiconductor substrate. A source electrode 32 and a drain electrode 33 are disposed on the semiconductor subtsrate 31. A spacer film 41 is disposed on the entire surface on the substrate and on electrodes 32 and 33. A photoresist film 43 is disposed on the spacer film 41. A window 43 is opened in the photoresist 42. A first aperture 44 is opened in the spacer film 41 by etching utilizing the window 43 of the of the photoresist film 42 as a mask. A concave portion 45 is produced in the substrate 31 by etching through the window 43 and the first aperture 44. A second aperture 46 is produced in the spacer film 41 by again etching the spacer film 41 through the window 43 of the photoresist 42. A first stage recess 47 is produced on the substrate 31 by etching through the window 43 and the second aperture 46. Then, a second stage recess 48 is produced at the center of the first stage recess 47 on the substrate 31. A gate electrode 49 is produced on the second stage recess 48.
As shown in FIG. 5(a), a source electrode 32 and a drain electrode 33 are deposited on the main surface of semiconductor substrate 31 with a predetermined distance therebetween. A spacer film 41 is deposited over the main surface of the semiconductor substrate 31 and the surfaces of the source and drain electrodes 32 and 33. The spacer film 41 is a silicon nitride film or a silicon oxide film. This spacer film 41 can be etched by a second etching solution which is different from the first etching solution for etching the semiconductor substrate 31.
Next, as shown in FIG. 5(b) a photoresist film 42 is deposited on the surface of the spacer film 41. A window having a pattern corresponding to the pattern of the gate electrode is disposed on a portion of the photoresist film 42 corresponding to a portion of the semiconductor substrate 31 where a gate electrode is to be produced between the source electrode 31 and the drain electrode 33.
Next, as shown in FIG. 5(c), using the photoresist 42 having a window 43 as a mask, a first aperture 44 having a pattern corresponding to the pattern of the window 43 is produced in the spacer film 41 by etching utilizing the second etching solution.
Next, as shown in FIG. 5(d), a concave portion 45 for producing a second recess is produced at the main surface portion of the semiconductor substrate 31 by etching utilizing the first etching solution with the spacer film 41 having a first aperture 44 as a mask.
Next, as shown in FIG. 5(e), a second aperture 46 having a pattern corresponding to the pattern of the first stage recess is produced by expanding the pattern of the first aperture 44 at the spacer film 41 by etching utilizing the second etching solution with the photoresist film 42 having the window 43 as a mask.
Next, as shown in FIG. 5(f), a first stage recess 47 having a pattern corresponding to a pattern of the second aperture 46 is produced at a portion of the main surface of the semiconductor substrate 31 by etching utilizing the first etching solution with the spacer film 41 having the second aperture portion 46 as a mask. At the same time, a second stage recess 48 corresponding to the pattern of concave portion 45 is produced at a portion of the bottom surface of the first stage recess 47.
Finally, as shown in FIG. 5(g), a gate electrode metal film is deposited on the surface of the photoresist film 42 having a window 43 and on the bottom surface of the second stage recess 48. The photoresist film 42 is removed together with the gate metal film on the surface thereof by lift-off, thereby producing a gate electrode 49 on the bottom surface of the second stage recess 48, completing an element having a two stage recess structure.
In the semiconductor device according to the above-described production method, the gate electrode can be produced in a two stage recess structure, and concentration of electric field at the recess edges is relaxed, thereby increasing the breakdown voltage of the device.
In the prior art production method, however, since the gate electrode is produced at the central portion of the recess, the gate-to-source distance is equal to the gate-to-drain distance. Therefore, an enhancement of the drain breakdown voltage leading to an enhancement in RF performance and a reduction in the gate-to-source capacitance and the source resistance cannot be accomplished at the same time. Further, according to such a production method, the gate electrode has a trapezoidal configuration and it is quite difficult to produce a gate shorter than 0.5 micron in length. Further, it is necessary to use an electron beam (EB) or focused ion beam (FIB) in order to miniaturize the gate length, thereby resulting in a problem in mass production. Further, in such a gate electrode structure, the gate cross-sectional area is reduced, which makes reduction of the gate resistance difficult. Further, according to the above-described production method, the width of the first stage recess 47 is determined by the degree of side etching of the spacer film 41 in the process of FIG. 5(e). The desired end point of the side etching is difficult to detect because at that end point the side wall is located below the photoresist 42 which results in difficulty in etching with high controllability and high reproducibility. Thus, there are many restrictions on enhancement of the breakdown voltage and performance in the prior art semiconductor device and in the production method therefor, and, therefore, it has been difficult to enhance the reverse gate breakdown voltage and to reduce the gate resistance and gate-to-source parasitic resistance simultaneously.